The manufacture of integrated circuits (ICs) usually adopts multilevel interconnects to build up 3-D interconnection structures in highly dense devices, as IC device performance extends to higher levels. In devices, the metal lines of the first layer are generally electrically coupled to the drains/sources of devices through vias, and the interconnects between the devices are coupled by the metal lines of other layers. On the other hand, the multilevel interconnects between the metal lines are separated by inter-metal dielectric (IMD) layers, while the respective metal layers are connected by via plugs. The dual damascene process is currently developed for forming via plugs and metal interconnects at the same time.
As to the metals, copper is gradually being substituted for aluminum, because copper comprises the properties of a high melting point and a low resistance (about 1.7 μΩ-cm), and is more capable of preventing electro-migration. However, copper itself is inclined to oxidize and tends to react with other materials at low temperatures. Further, no effective dry etching process exists for copper. Nevertheless, these issues are overcome by improved diffusion barrier materials and progressive processes, such as damascene process, and chemical mechanical polishing (CMP).
FIGS. 1A–1E illustrate a conventional method of manufacturing dual damascene. Referring to FIG. 1A, a semiconductor substrate 101 with a plurality of semiconductor devices (not shown) is provided. A metal layer 103, a first etching stop layer 107, an inter-metal dielectric layer 109, and a second etching stop layer 111 are subsequently formed thereon. A photoresist layer 113 is then coated and patterned to define the position of a via.
The via 116 is formed by etching the second etching stop layer 111, the inter-metal dielectric layer 109, and the first etching stop layer 107, as illustrated in FIG. 1B. In this step, the metal layer 103 has been exposed to air. As a result, a baking step should now be performed to prevent the metal layer 103 oxidation. After that, a sacrificial layer 115 is filled therein.
In turn, the sacrificial layer 115 is etched back, and a photoresist layer 117 is next coated thereon, as shown in FIG. 1C. Referring to FIG. 1D and FIG. 1E, the photoresist layer 117 is patterned and etched to form a trench 118. After the photoresist layer 117 and the sacrificial layer 115 are removed, a metal layer 119 is then filled therein.
According to the aforementioned description, the conventional method for manufacturing dual damascene is to form a trench following a via. This method, however, conceals some problems. As mentioned above, the metal layer 103 has been exposed to air before the sacrificial layer 115 is filled therein. Using copper as the metal layer dramatically affects the quality of the devices, since copper is inclined to oxidize. Therefore the queue time (Q-time) should be controlled precisely.
Moreover, micro trenches 203 and fences 201 issues commonly occur in the conventional process, as shown in FIG. 2, that affect the subsequent processes. For example, fences cause poor coverage capability of barrier layers and electrochemical plating (ECP) deposition. Fences, for instance, further result in unsteady electrical properties, as well as poor reliability of devices.
In addition, the dielectric layer 109 is generally constituted by porous low-k materials, through which residual NH-group components in the substrate readily pass to neutralize with the photoresist layer, and consequently react to be photoresist scum. Therefore the photoresist is not developed and patterned well, which also leads to a decrease in the production yield.